Purchasers of telecommunications systems are highly influenced by the reliability of these systems. In fact, for most users of high-speed telecommunications systems, high reliability is essential. Consequently, designers of telecommunications systems commonly use redundant components and circuits to increase the reliability of their systems. For example, if a fault develops in a critical portion of the system, then the redundant component or circuit automatically takes over the function of the faulty portion. Alternatively, and also by way of example, a user may switch an operation to a redundant component or circuit for maintenance purposes. Subsequently, the primary component or circuit may be replaced by a new part. In order to maximize maintainability and minimize fabrication costs, manufacturers of high-speed telecommunications systems typically provide interchangeable primary and redundant components or circuits.
In a known configuration, which will be described in detail below, a plurality of primary stratum clock modules and redundant, "hot standby" stratum clock modules are included in a high-speed telecommunications system. These stratum clock modules are used to provide the clock pulses required to synchronize certain discrete, integrated circuits that make up the system. Typically, the primary and standby stratum clock modules are interchangeable as to both location and function. Consequently, if the quality of a primary clock's signals degrades significantly, or the operation of the primary clock is disrupted, then the system switches operational use over to a standby clock module. If deemed necessary, the user may then replace the defective module with a new module. Given the interchangeability of the primary and standby modules, and the current state of the technology, frequency errors between the primary and standby clock signals can be minimized. Therefore, by providing redundant stratum clock modules, the manufacturer ensures that the operability and reliability of the overall system is increased. However, although the frequencies of the primary and standby clock signals can be aligned to within an acceptable tolerance, a significant phase difference between the two signals can still exist. Consequently, when operations are switched from one clock module to another, if a phase difference between the two clock signals exists, a transient is generated along with the clock signal and propagated throughout the system. So, for a significant period of time after the switching operation, portions of the system will be out of synchronization, and the performance and reliability of the overall system will be degraded.
In a known configuration, an exclusive-or (XOR) gate is included as a phase detector to detect and measure phase differences between high-speed signals. However, under certain conditions, the binary waveforms present at the inputs of the XOR phase detector may overlap for less than a 50% duty cycle, which limits the detection range of such XOR phase detectors to within 180.degree.. Another known phase detector includes a pair of interconnected D-type flip-flops configured to provide a detection range of 360.degree., but the gain of this circuit becomes nonlinear (i.e., produces a dead band) as the detected phase difference approaches 0.degree. (or 360.degree.). Consequently, the limited performance characteristics and inaccuracies of these phase detectors make them unacceptable for high-speed clock signal, phase-alignment applications.
It is an object of the present invention, therefore, to provide a method and system that accurately detects and measures a phase difference, linearly over a range of 360.degree., between the output signals from a primary stratum clock module and a standby stratum clock module in a telecommunications system, calculates the amount of time needed to delay the standby clock signal enough to cancel the phase difference, and controls a digital delay line to shift the phase of the standby clock signal accordingly and thereby cancel the phase difference. Both the frequency and phase alignments of the two clocks are thus maintained. Therefore, when the system or user switches operations from the primary stratum clock module to the standby stratum clock module, phase-related transients are not generated, which results in a significant increase in the overall performance and reliability of the system. The present invention achieves this object with minimal additional circuitry.